Conventional multi-core processors include two or more processing units integrated on an integrated circuit die or onto multiple dies in a chip package. These processing units are referred to as “CPU cores” or “cores.” The cores of a multi-core processor may all run a single OS, with the workload of the OS being divided among the cores. This configuration, where the cores run the same OS, is referred to as symmetric multiprocessing (SMP).
SMP delivers the advantage of additional processing power. In particular, SMP offers significant performance benefits for heavy workloads by distributing operations among the cores. However, each operation that is divided between the cores increases the complexity of the processing of the operations, which increases latency. Latency, which may also be referred to as “response time,” may refer to the time taken to complete an operation. Latency for operations divided between multiple cores may be increased due to processing overhead relating to the dividing of the operations between the cores. For example, latency may be increased by additional processing overhead of resource contention management mechanisms.
In contrast to latency is throughput. Throughput may refer to the average rate at which operations are completed. Providing multiple cores may allow for additional operations to be processed in parallel, thereby resulting in a performance benefit of increased throughput at the cost of increased latency. Thus, there is a trade-off between low latency for individual operations versus high throughput.
Accordingly, the potential remains for improvements that, for example, realize the performance benefits of a multi-core architecture while reducing latency.